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full_adder.v
1
module full_adder(
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input a, b, cin,
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output sum, cout
4
);
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assign {cout, sum} = a + b + cin;
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endmodule
WAVEFORM SIMULATION
clk
sum
SYNTHESIS LOG

Successfully compiled 'full_adder.v' (0.04s)

Analyzing module <full_adder>...

Synthesizing Unit <full_adder>...

Found 1-bit adder for signal <sum>

Summary:

LUTs: 2 | FlipFlops: 0 | Latches: 0

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